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Electrical drawing – source data

This document collects all electrical data needed to wire the system and to design a future PCB. It is the source for the schematic set schematics/load_cell_wiring.pdf (drawing no. LC-E-001), which is generated by schematics/generate_wiring_schematic.py.

Status: preliminary. Items marked (Ön) refer to open items in 03 – Check list. Nothing here is verified by measurement yet.

Sources used:

Source Used for
load-cell-click-schematic-v100.pdf (MIKROE) Click internal circuit, mikroBUS pins, terminal blocks, JP1
HX711 datasheet.pdf (Avia) Pins, supply ranges, input range, timing
ESP32-P4-WIFI6-POE-ETH-Schematic.pdf (Waveshare) Header P6, DSI J1, power tree, on-board GPIO use
esp32-p4_datasheet_en.pdf v0.7 (Espressif) GPIO restrictions, strapping pins, logic levels
Gefran_TU_Datasheet.pdf Load cell data, wire colours, screen
MIKROE product page Load cell click (MIKROE-3168), incl. product photo mikroBUS pinout, printed pin labels, VCC SEL default
Waveshare docs ESP32-P4-WIFI6-POE-ETH (pinout diagram, board photo) Labels of header P6, 5 V terminal J6
Waveshare wiki 10.1-DSI-TOUCH-A Display power, touch IC, backlight control

The project files Waveshare 10.1-DSI-TOUCH-A.pdf, ESP32-P4-WIFI6-POE-ETH.pdf and the MIKROE page screenshot PDF contain no readable text layer; the same pages were read directly from the manufacturers' websites (2026-10-13).

Printed labels. Text in quotes, e.g. "RTE", is the marking printed on the board next to the contact. It is shown on the schematic, the connector sheet and the wiring list so the wiring can be followed directly on the boards.


1. Schematic set LC-E-001

Sheet Content
1 Cover, sheet index, reference designations, notation
2 System overview (block diagram, cables, key figures)
3 Measurement circuit: load cell → Load cell click → ESP32-P4 header
4 Power supply (USB-C / PoE, 5 V and 3.3 V rails) and display connection
5 Connector views (face views with pin numbers)
6 Wiring list

Regenerate after any change:

cd schematics
python3 generate_wiring_schematic.py load_cell_wiring.pdf

Requires Python 3 and reportlab.


2. Reference designations

Per SS-EN IEC 81346-2:2019, two-letter class codes. The class codes other than -KE1 (given as example in 01 – Overview) are a proposal and must be confirmed against the standard's tables (Ö9).

Designation Item Note
-BW1 Load cell, Gefran TU-K2C 0–200 kg, S/N 26390078 Class code to confirm (Ö9)
-TF1 Signal converter, MIKROE Load cell click (HX711) Class code to confirm (Ö9)
-KE1 Control board, Waveshare ESP32-P4-WIFI6-POE-ETH
-PH1 Display, Waveshare 10.1-DSI-TOUCH-A Class code to confirm (Ö9)
-WG1 Load cell cable, 4 × 0.25 mm² + screen, 5 m (integral to -BW1)
-WG2 Jumper wires -TF1 ↔ -KE1, 6 × Dupont female/female
-WG3 DSI flat cable, -KE1:J1 (15-pin) ↔ -PH1 Display-side connector to confirm (Ö6)
-WG4 Display power cable, 2-wire RD/BK, supplied with -PH1

Notation: -KE1:P6.14 = device -KE1, connector P6, contact 14. Manufacturer designators (P6, J1, TB1, JP1, U1, R2 …) are kept as printed on the boards.


3. Load cell – -BW1 Gefran TU-K2C

Parameter Value
Bridge Full Wheatstone bridge, 350 Ω in / 350 Ω out
Sensitivity 2 mV/V at nominal load (200 kg)
Zero balance < ±1 % FSO
Nominal / max supply 10 V / 15 V
Isolation resistance > 10 GΩ
Signal sign Tension: positive, compression: negative
Cable Screened, 4 × 0.25 mm², 5 m
Screen Isolated from the body; earth at the instrument end only

Wire colours (Gefran datasheet). The datasheet gives the pairs but not the +/− polarity inside each pair (Ö1). The assignment below is provisional and is used in the drawing until Ö1 is closed:

Colour (IEC 60757) Function Provisional polarity
WH white Excitation EXC+
GN green Excitation EXC−
RD red Signal SIG+
YE yellow (or BK black) Signal SIG−
GNYE green-yellow Screen –

A swapped pair does not damage the cell or the HX711; it only inverts the sign of the reading. If tension reads negative after wiring, swap the signal pair (or the excitation pair) in the terminal block, or invert the sign in firmware, and record which was done.


4. Signal converter – -TF1 MIKROE Load cell click

4.1 Internal circuit (from MIKROE schematic v100)

Ref. Part Function
U1 HX711, SOP-16 24-bit ΣΔ ADC with PGA
Q1 MMBT3906 (PNP) Pass transistor for the AVDD / excitation regulator
R1, R3 20 kΩ, 8.2 kΩ Regulator feedback divider (VFB)
R2, R4 100 Ω Series resistors, channel A (SA+ / SA−)
C6 100 nF Differential filter capacitor, channel A
R5, R6, C8 100 Ω, 100 Ω, 100 nF Same filter for channel B (not used)
C1, C2, C3 10 µF, 100 nF, 100 nF Decoupling VCC-5 / VCC
C4, C5 10 µF, 100 nF Decoupling EX+ (AVDD)
C7 100 nF VBG reference bypass
JP1 SMD jumper, printed "VCC SEL", pads "3V3" (left) / "5V" (right) Selects the DVDD rail: 1 = VCC-3.3, 2 = VCC (common), 3 = VCC-5. MIKROE default: left (3V3)
LD1, R7 Green LED, printed "PWR", 1.5 kΩ Power indicator on VCC-5
TB1, TB2, TB3 2-pole screw terminals Excitation, input A, input B

HX711 pin use on the click:

Pin Name Connected to
1 VSUP VCC-5 (+5V on mikroBUS) – always 5 V
2 BASE Q1 base
3 AVDD EX+ (Q1 collector)
4 VFB R1/R3 divider
5 AGND GND
6 VBG C7 to GND
7 INNA SA− via R4 from TB2.1
8 INPA SA+ via R2 from TB2.2
9 INNB SB− via R6 from TB3.1
10 INPB SB+ via R5 from TB3.2
11 PD_SCK CLK → mikroBUS PWM (pin 16), printed "CLK"
12 DOUT DO → mikroBUS INT (pin 15), printed "DO"
13 XO Not connected
14 XI GND (internal oscillator)
15 RATE RTE → mikroBUS CS (pin 3), printed "RTE" (no pull resistor on the board)
16 DVDD VCC (JP1 common)

4.2 Printed labels on the click (product photo, terminals at the top)

Location Printed labels
Terminal blocks, left to right "EX+" "GND" (TB1), "SA+" "SA-" (TB2), "SB+" "SB-" (TB3)
Left pin row, top to bottom (mikroBUS 1–8) "NC" "NC" "RTE" "NC" "NC" "NC" "3V3" "GND"
Right pin row, top to bottom (mikroBUS 16–9) "CLK" "DO" "NC" "NC" "NC" "NC" "5V" "GND"
Jumper "VCC SEL", pads "3V3" (left) and "5V" (right)
LED "PWR"

Correction: the MIKROE pinout table and the printed "RTE" at the third pin both place RTE on mikroBUS CS (pin 3). Rev A of this drawing and 02 – Component list had it on RST; this is corrected in rev B. The schematic PDF line for RTE runs between RST and CS, which is why it was misread.

4.3 Supply and levels

  • VSUP is always fed from the +5V pin. The 5 V wire is required even when the logic runs at 3.3 V.
  • Excitation / AVDD: V_AVDD = VBG × (1 + R1/R3) = 1.25 V × (1 + 20/8.2) = 4.30 V. This matches the "approx. 4.3 V" in 02 – Component list. The HX711 datasheet requires AVDD at least 100 mV below VSUP: 5.0 V − 4.30 V = 0.70 V margin, minus the Q1 drop.
  • Logic level: DVDD is selected by JP1 ("VCC SEL"). With the bridge on the left pair ("3V3"), DOUT is 3.3 V logic and can go directly to the ESP32-P4. On the right pair ("5V"), DOUT would be 5 V logic, which exceeds the ESP32-P4 limit (VDD + 0.3 V, abs. max. 3.6 V). MIKROE states the default is left (3V3); check the actual board (Ö4).
  • Grounding: AGND and GND are the same net on the click. TB1.1 is GND (E−). There is no dedicated screen terminal (Ö7).

4.4 Measurement range

Quantity Value
Full-scale bridge output at 200 kg 2 mV/V × 4.30 V = 8.6 mV
HX711 channel A input range, gain 128 ±0.5 × AVDD / 128 = ±16.8 mV (±20 mV only applies at AVDD = 5 V)
Use of the input range at 200 kg 8.6 / 16.8 ≈ 51 %
Headroom Covers 130 % static load (11.2 mV) and the ±1 % zero offset
Input common-mode range AGND + 1.2 V … AVDD − 1.3 V = 1.2 … 3.0 V; bridge mid-point ≈ 2.15 V, OK
LSB size 2 × 16.8 mV / 2²⁴ ≈ 2 nV; real resolution is noise-limited (input noise 50 nV rms at 10 SPS, 90 nV rms at 80 SPS)

4.5 Serial interface (for firmware)

Moved to 05 – Software, section 5.2.


5. Control board – -KE1 Waveshare ESP32-P4-WIFI6-POE-ETH

5.1 Header P6 (2 × 20, 2.54 mm)

Pin numbering is taken from the Waveshare schematic symbol P6, and the Waveshare pinout diagram agrees with it: pins 1 and 3 are "5V", pins 2 and 18 are "3V3". This differs from the Raspberry Pi convention (pin 1 = 3V3). The header itself is only marked "1", "2" and "GPIO" on the board; the labels below are those of the Waveshare pinout diagram. Measure the voltages before connecting wires (Ö5).

Pin Net Pin Net
1 "5V" VCC_5V 2 "3V3" ESP_3V3
3 "5V" VCC_5V 4 "SDA/GPIO7" (I²C, shared)
5 "GND" 6 "SCL/GPIO8" (I²C, shared)
7 "TXD/GPIO37" (UART0) 8 "GPIO23"
9 "RXD/GPIO38" (UART0) 10 "GND"
11 GPIO22 12 GPIO21
13 GND 14 GPIO20
15 GPIO5 16 GPIO6 (also C6_IO2 via R52)
17 GPIO4 18 ESP_3V3
19 GND 20 GPIO3
21 GPIO1 22 GPIO2
23 GPIO36 (strapping, 10 k pull-up R41) 24 GPIO0
25 GPIO32 26 GND
27 GPIO25 (USB Serial/JTAG) 28 GPIO24 (USB Serial/JTAG)
29 GND 30 GPIO33
31 GPIO54 (C6_CHIP_PU via R54) 32 GPIO26
33 GND 34 GPIO48
35 GPIO46 36 GPIO53 (PA_CTRL, speaker amp)
37 GPIO27 38 GPIO47
39 GPIO45 (SD card power switch) 40 GND

The 5 V rail on P6 has TVS diode D1 (SMF5.0CA) to GND.

5.2 GPIO assignment for the HX711

Signal HX711 pin Click (mikroBUS) ESP32-P4 GPIO P6 pin Direction
CLK / PD_SCK 11 PWM (mB.16), printed "CLK" GPIO20 14 Output
DO / DOUT 12 INT (mB.15), printed "DO" GPIO21 12 Input
RTE / RATE 15 CS (mB.3), printed "RTE" GPIO22 11 Output

Reasons for the choice (Ö8):

  • GPIO20–22 are priority-2 pins in the ESP32-P4 datasheet (no restrictions), in the VDD_IO_0 domain, and are not used by any other circuit in the Waveshare schematic.
  • Avoided: GPIO7/8 (I²C to touch and codec), GPIO9–13 (I²S codec), GPIO14–19 and GPIO6/54 (ESP32-C6 SDIO), GPIO24–27 (USB), GPIO28–36, 49–52 (Ethernet RMII / strapping), GPIO34–38 (strapping, UART0), GPIO39–45 (SD card), GPIO53 (speaker amplifier).
  • GPIO20–22 are next to each other on P6 (pins 11, 12, 14) close to GND (pin 10) and the supply pins, which keeps the jumper wires short and tidy.

Notes:

  • Behaviour of GPIO20 and GPIO22 at start-up (they float until firmware drives them): see 05 – Software, section 5.2.
  • Logic thresholds at 3.3 V: V_IH ≥ 0.75 × VDD = 2.48 V, V_IL ≤ 0.25 × VDD = 0.83 V.

5.3 Power tree (from Waveshare schematic)

Rail Source Notes
Type_C_5V USB-C connector USB1 TVS1 LTVS16H5.0ET5G, CC1/CC2 5.1 kΩ (sink, 5 V)
VCC_5V Type_C_5V via Q2 AO3401 / U13 MMDT3906DW, or PoE module output (PoE header pin 4) Feeds P6.1/P6.3 (P6.1 = display W22, P6.3 = click W11), the 2-pin terminal J6 (printed "5V"/"GND") and the 3.3 V buck
ESP_3V3 U3 MP1658GTF-Z buck from VCC_5V, L1 4.7 µH 3 A max; feeds ESP32-P4, P6.2/P6.18 and DSI J1.14/15

5.4 DSI connector J1 (15-pin, Pi 4B type)

Pin Net Pin Net
1 GND 9 DSI_D0_P
2 DSI_D1_N 10 GND
3 DSI_D1_P 11 ESP_I2C_SCL (GPIO8)
4 GND 12 ESP_I2C_SDA (GPIO7)
5 DSI_CLK_N 13 GND
6 DSI_CLK_P 14 ESP_3V3
7 GND 15 ESP_3V3
8 DSI_D0_N

The touch controller shares the I²C bus GPIO7/GPIO8 with the audio codec U10 (ES8311).


6. Display – -PH1 Waveshare 10.1-DSI-TOUCH-A

Data from the Waveshare wiki (10.1-DSI-TOUCH-A):

Item Value
Power input 5.00 V (4.75–5.30 V), 0.8 A typical; below 0.8 A the display may fail to start
Power connection Separate 2-pin power connector with a 2-wire cable (red / black). On a Raspberry Pi it plugs onto the 5 V / GND header pins – power is not taken from the DSI cable
Video MIPI-DSI 2 lanes; ESP-IDF driver component waveshare/esp_lcd_jd9365_10_1
Touch GT9271 (Goodix), I²C
Backlight Set by writing 0x00–0xFF to register 0x86 of I²C device 0x45 (as given for ESP32-P4)

Connection in this project:

  • Video and touch: -KE1:J1 → -WG3 → -PH1 DSI connector. The cable must be the 15-pin type at the -KE1 end (J1 is a Raspberry Pi 4B style 15-pin, 1 mm). The display-side connector and the exact cable are to be confirmed (Ö6).
  • Power: -WG4 red → -KE1:P6.1 ("5V"), black → -KE1:P6.5 ("GND"). Pins 1 and 5 are not adjacent (P6.3 "5V" with W11 sits between them), so the cable cannot be plugged on as a two-pin block; use separate leads. The 2-pin terminal J6 ("5V"/"GND") is on the same VCC_5V net and is an alternative.
  • The 5 V source (USB-C or PoE) must supply the display's 0.8 A plus the board. The board's own consumption is not documented (Ö6).

7. Wiring list

Wire Cable From Signal To Signal Type / colour mm² Note
W01 -WG1 -BW1 lead WH EXC+ (prov.) -TF1:TB1.2 "EX+" EX+ / AVDD WH 0.25 Ö1
W02 -WG1 -BW1 lead GN EXC− (prov.) -TF1:TB1.1 "GND" GND GN 0.25 Ö1
W03 -WG1 -BW1 lead RD SIG+ (prov.) -TF1:TB2.2 "SA+" A+ / SA+ RD 0.25 Ö1
W04 -WG1 -BW1 lead YE/BK SIG− (prov.) -TF1:TB2.1 "SA-" A− / SA− YE or BK 0.25 Ö1
W05 -WG1 -WG1 screen Screen -TF1:TB1.1 "GND" GND GNYE – Ö7, shares terminal with W02
W11 -WG2 -TF1:mB.10 "5V" +5V -KE1:P6.3 "5V" VCC_5V Dupont F/F, RD AWG26 Ö5
W12 -WG2 -TF1:mB.7 "3V3" +3.3V -KE1:P6.18 "3V3" ESP_3V3 Dupont F/F, OG AWG26 Ö5
W13 -WG2 -TF1:mB.8 "GND" GND -KE1:P6.19 "GND" GND Dupont F/F, BK AWG26
W14 -WG2 -TF1:mB.16 "CLK" PWM = CLK -KE1:P6.14 "GPIO20" GPIO20 (out) Dupont F/F, YE AWG26 Ö8
W15 -WG2 -TF1:mB.15 "DO" INT = DO -KE1:P6.12 "GPIO21" GPIO21 (in) Dupont F/F, GN AWG26 Ö8
W16 -WG2 -TF1:mB.3 "RTE" CS = RTE -KE1:P6.11 "GPIO22" GPIO22 (out) Dupont F/F, BU AWG26 Ö8
W21 -WG3 -KE1:J1.1–15 MIPI-DSI, I²C, 3V3 -PH1 DSI – DSI FPC, 15-pin at -KE1 – Ö6
W22 -WG4 -PH1 power, RD +5 V -KE1:P6.1 "5V" VCC_5V cable RD (supplied) – Ö6
W23 -WG4 -PH1 power, BK GND -KE1:P6.5 "GND" GND cable BK (supplied) – Ö6

Jumper-wire colours are a suggestion; keep this list updated if others are used. mikroBUS GND pins 8 and 9 are joined on the click, so one GND wire is enough.

Connection procedure

  1. Check that the -TF1 "VCC SEL" bridge is on the left pair ("3V3") (Ö4).
  2. Power -KE1 alone. Measure P6.3 and P6.18 against P6.19: expect 5 V and 3.3 V (Ö5). Power off.
  3. Fit ferrules on the load cell leads and connect W01–W05 to TB1/TB2.
  4. Connect W11–W16, then the display power cable W22/W23 and the DSI cable W21.
  5. Power on with a 5 V supply rated for the display. Measure "EX+" against "GND" on TB1: expect approx. 4.3 V. Measure "SA+" against "SA-" with no load: expect close to 0 mV (within ±0.09 mV, ±1 % FSO zero balance).
  6. Apply tension and check that the reading increases. If not, see section 3.

8. Data for future PCB design

The goal is a carrier PCB that replaces the click and the jumper wires. The data below is collected from the sources; the values are what the current click uses unless marked otherwise.

8.1 Circuit blocks to carry over

Block Design basis
ADC HX711 SOP-16, internal oscillator (XI to GND, XO open)
Excitation regulator PNP pass transistor (MMBT3906 on click, S8550 in HX711 reference design), R1 20 kΩ / R3 8.2 kΩ → 4.30 V; 10 µF + 100 nF at AVDD
VSUP 5 V from the board's VCC_5V; keep ≥ 100 mV above AVDD plus transistor drop
DVDD 3.3 V from ESP_3V3 (same supply as the MCU, as the HX711 datasheet recommends) – no jumper needed
Input filter 100 Ω in series in each signal line, 100 nF across the pair at the HX711 pins
VBG 100 nF to AGND
RATE Strap with a resistor (pull-down = 10 SPS) or a GPIO with defined default; do not leave floating
PD_SCK Add a pull-down (e.g. 10 kΩ, value to be chosen) so the HX711 is defined during MCU reset
Channel B Not used – the HX711 datasheet gives no rule for unused inputs; decide during PCB design (e.g. tie to a defined level)

8.2 Load and ratings

Item Value
Bridge current 4.30 V / 350 Ω ≈ 12.3 mA
HX711 analog incl. regulator ≈ 1.4 mA
HX711 digital ≈ 0.1 mA
Total from 5 V (without LED) ≈ 14 mA
PNP dissipation (5.0 − 4.30) V × 12.3 mA ≈ 9 mW

8.3 Layout rules

  • Keep the HX711 input traces (INPA/INNA) short, routed as a pair, and away from the DSI, Ethernet and switching-regulator areas of the control board.
  • Solid ground plane; connect AGND and GND at one point near the HX711.
  • Place the filter capacitor and VBG/AVDD decoupling close to the HX711 pins.
  • Load cell connector: 5 positions (EXC+, EXC−, SIG+, SIG−, screen). Connect the screen to GND at this end only. Consider ESD/TVS protection on the four bridge lines if the cable is exposed.
  • Logic connection to the ESP32-P4: CLK, DOUT, RATE, 5 V, 3.3 V, GND – same as the jumper-wire version, so firmware does not change.

8.4 Open points before PCB layout

Ö1 (polarity), Ö4 (logic level, settled by design on the PCB), Ö5 (header pin 1), Ö6 (display connection) and Ö7 (screen termination) should be closed first. Ö8 (GPIO choice) is closed: the pins work on the board (2026-10-16).


9. Files to update when wiring or I/O changes

  • docs/04-electrical_drawing.md (this file)
  • schematics/generate_wiring_schematic.py and regenerate schematics/load_cell_wiring.pdf
  • docs/02-componet_list.md if a component or its key data changes
  • docs/03-check_list.md for new or closed items
  • Firmware pin definitions: include/load_cell_config.h (see 05 – Software)